1. Field
Example embodiments of the inventive concepts relate to methods of manufacturing semiconductor devices, and more particularly, to methods of manufacturing semiconductor devices including contact holes of different sizes formed using a single photolithography process.
2. Description of Related Art
In recent years, demand for high-capacity semiconductor memory devices, especially high-capacity dynamic random access memories (DRAMs), has been ever increasing. However, there is a specific technical limit to increasing the capacity of DRAM devices due to increasing chip size. An increase in chip size may lead to a reduction in the number of chips per wafer, thereby reducing productivity. Thus, many attempts are being made at varying a cell layout to reduce a cell area so that the greatest possible number of memory cells may be integrated on a single wafer. As a result, a conventional 8F2 layout may be gradually superseded by a 6F2 layout.
However, since a semiconductor memory device having a 6F2 DRAM cell has an interval of only 1F between active regions, a contact area between a BC contact and a BC storage contact pad may become vulnerable when misaligned. Furthermore, the BC contact may be brought into contact with its adjacent DC bit line contact pad, thereby causing a short.